Many electronic devices, including portable devices, enable the use of mass memory components.
The actual access to such a mass memory component for reading and writing operations is usually controlled by an ASIC (Application Specific Integrated Circuit) in the electronic device. The ASIC comprises to this end a memory controller, the functionality of which is implemented partly with software and partly with hardware, and a bus connected on the one hand to the memory controller and on the other hand to interface pins of the ASIC. The term memory controller is used in this document for referring to an entity which provides memory interface functions between a CPU (central processing unit) and a memory. The memory bus is not included in this memory controller. The bus in the ASIC is employed for transferring control signals and data to and from a mass memory component connected to the interface pins under the control of the memory controller using a dedicated interface protocol. The mass memory component can be an internal mass memory component, which is integrated into the electronic device and connected to the interface pins. Alternatively, the mass memory component can be an external mass memory component, which is connected to the interface pins via an external interface of the electronic device.
Most known approaches have the disadvantage that the employed ASIC is designed exclusively for a specific implementation of the electronic device. Thus, the possibilities of employing the ASIC are rather limited.
In one more flexible known approach, the ASIC comprises a narrow bus to which two mass memory components can be connected in parallel via the interface pins of the ASIC. But the ASIC considers the memory components as a single memory component. The reading and writing operations are carried out for all of the memory components at the same time, not separately. This prevents for example that data provided by the electronic device is stored in a specific one of the memory components for later use with some other electronic device. Moreover, this implementation of the ASIC allows only the use of either two external memory components or two internal memory components, not the simultaneous use of an internal and an external memory component.
In another known approach, some interface pins of an ASIC which are provided for an interface associated to a first interface protocol are used in addition for an interface associated to a second interface protocol. If a large number of pins is used for one of the interfaces, then there is only a small number of interface pins left for the other interface, and it is not possible to use large memory components with this other interface, since there are not enough interface pins for supporting a large memory component. It is moreover a disadvantage of this approach that a different interface protocol is used for each interface and that each interface protocol requires a dedicated bus in the ASIC.